The present invention relates to the synchronism control of a viterbi decoder.
In recent years, data transmission by satellite communications and cable has been digitized. In such digitized data transmission, a punctured code is used to realize high-speed data transmission with high error correction capability in a limited frequency band.
On the transmitting side, in compliance with a fixed pattern from a code group of a multiplex code created at a coding rate 1/2, the code is deleted to create a punctured code at a coding rate of n/m (n less than m), which is modulated by a digital modulator and transmitted to the receiving side.
On the receiving side, a signal which has been demodulated by a demodulator is error-corrected using a viterbi decoder and output.
The viterbi decoder corrects errors in the demodulated signal by inserting a dummy symbol into the signal output from the demodulator.
The viterbi decoder monitors the number of bits corrected by counting the number of bit errors corrected in a fixed period.
When the insertion position of the dummy symbol is incorrect, i.e. when there is asynchronism, the value of the bit error constant which is monitored by the viterbi decoder becomes large. On the other hand, when the insertion position of the dummy symbol is correct, i.e. when there is synchronism, the value of the bit error constant decreases.
The viterbi decoder determines whether there is asynchronism or synchronism by comparing the number of bit error corrections with a predetermined threshold.
The number of positions where the dummy symbols are inserted is determined based on the coding rate. The viterbi decoder searches for synchronism by shifting the positions in each measurement period and comparing the number of bit error corrections in each aspect with the threshold.
FIG. 12 shows a sequence for creating a punctured code having a coding rate of 3/4 used in QPSK, and FIG. 11 is a block diagram of a conventional viterbi decoder.
As shown in FIG. 12, the punctured code is created by a multiplex coder having a coding rate of 1/2 and a symbol selector.
When a one-bit information group, . . . , i0, i1, i2, . . . has been input into the multiplex coder, the multiplex coder outputs a two-bit coded group, . . . , (X11, Y11), (X12, Y12), (X13, Y13) . . .
The symbol selector outputs (X11, Y11), (X12, Y12), (X13, Y13) as one block after deleting the codes at predetermined positions.
FIG. 12 shows an example where the deleted pattern is (101, 110). As a consequence, (X11, Y11), (X12, Y12), (X13, Y13) becomes (X11, Y11), (Y13, X12), and this is output from the symbol selector to the modulator.
The conventional viterbi decoder comprises, as shown in FIG. 11, a phase rotator 1, a dummy symbol inserter 2, a viterbi decoding section 3, a multiplex coder 4, a delay circuit 5, a synchronism detector 6, and a measurement period counter 7.
The synchronism detector 6 outputs a phase changing signal CHPH to the phase rotator 1, and outputs a dummy symbol position changing signal CHPOS to the dummy symbol inserter 2.
These two signals adjust the positions at which the dummy symbols are to be inserted into the modulation signal.
The operation of each block of the viterbi decoder will be explained here.
The phase rotator 1 controls (Ixe2x80x2, Qxe2x80x2)=(I, Q) when the phase changing signal CHPH is xe2x80x9c0xe2x80x9d, and controls (Ixe2x80x2, Qxe2x80x2)=(Q, xe2x88x92I) when the phase change signal CHPH is xe2x80x9c1xe2x80x9d.
The dummy symbol inserter 2 changes the insertion position of the dummy symbol when the dummy symbol position changing signal CHPOS has charged.
As an example, FIG. 13A to FIG. 13D show the output of the dummy symbol inserter 2 when a punctured code at a coding rate of 3/4 has been transmitted.
When coding has-been carried out as explained above, the state in FIG. 13A is synchronized, but the states of FIG. 13B to FIG. 13D are asynchronized.
The viterbi decoding section 3 corrects errors in compliance with a viterbi algorithm based on the signal which is output from the dummy symbol inserter 2. The multiplex coder 4 codes the corrected output of the viterbi decoding section 3.
The delay circuit 5 delays the output of the dummy symbol inserter 2 by time T. This delay T is equal to the sum of the delay of the viterbi -decoding section 3 and the delay of the multiplex coder 4. When the output I and Q (omitted from the figure) of the demodulating section is an n-bit soft determining signal, the delay circuit 5 delays the MSB of Ixe2x80x2 and Qxe2x80x2.
The synchronism detector 6 compares the output of the delay circuit 5 with the output of the multiplex coder 4 and counts the number of bit error corrections. The synchronism detector 6 compares this number with an externally set threshold and determines whether the outputs are synchronized or asynchronized. That is, the synchronism detector 6 determines whether the dummy symbols have been inserted at the correct positions.
For example, for a demodulated signal at a coding rate of 3/4, the phase rotator 1 outputs (Ixe2x80x2, Qxe2x80x2)=(I, Q), and the output of the dummy symbol inserting circuit is as shown in FIG. 13B. Therefore, synchronism is controlled in the following way when the viterbi decoder starts correcting errors.
The viterbi decoded result is determined as asynchronized when the output of the dummy symbol inserter 2 is in the state shown in FIG. 13B.
Synchronism is achieved by using the phase rotator 1 to control of (Ixe2x80x2, Qxe2x80x2)=(I, xe2x88x92Q), or by changing the insertion position of the dummy symbol in the dummy symbol inserter 2.
When the insertion position of the dummy symbol has been changed, the input into the viterbi decoding section 3 changes from the states shown in FIG. 13B to that shown in FIG. 13D.
The viterbi decoded result is determined as asynchronized when the output of the dummy symbol inserter 2 is in the state shown in FIG. 13B.
The dummy symbol inserter 2 controls of (Ixe2x80x2, Qxe2x80x2)=(Q, xe2x88x92I). The input into the viterbi decoding section 3 changes from the state shown in FIG. 13B to that of FIG. 13C.
The viterbi decoded result is determined as asynchronized when the output of the dummy symbol inserter 2 is in the state shown in FIG. 13C.
The phase rotator 1 maintains (Ixe2x80x2, Qxe2x80x2)=(Q, xe2x88x92I) while the dummy symbol inserter 2 changes the insertion position of the dummy symbol. The input to the viterbi decoding section 3 changes from that shown in FIG. 13C to the one shown in FIG. 13A.
When the output of the dummy symbol inserter 2 is in the state shown in FIG. 13A, the viterbi decoded result is determined as synchronized.
Viterbi decoding is performed while maintaining the states of the phase rotator 1 and the dummy symbol inserter 2.
When asynchronism is detected, the phase rotator 1 controls of (Ixe2x80x2, Qxe2x80x2)=(I, Q) and the dummy symbol inserter 2 is returned to its-initial state prior to searching for synchronism.
The measurement period counter 7 controls the timing according to which the synchronism detector 6 compares the number of corrected bit errors with the threshold. The measurement period counter 7 is set externally.
In the synchronized state, a synchronism detecting signal is output to the synchronism detector 6 in each measurement period.
In the asynchronized state, a delay T is needed from the point where the output of the dummy symbol inserter 2 changes until a signal is input into the viterbi decoding section 3 and recorded.
In the asynchronized state, the measurement period counter 7 stops the time count during the period T from the change of the output of the dummy symbol inserter 2, and the synchronism detector 6 stops counting the number of bit error corrections.
When the coding rate changes on the transmission side, it is not possible to detect synchronism in the specified number of times by measuring the bits in an operation mode at a coding rate of 3/4. For this reason, the operating mode is changed at such times in order to detect synchronism.
Thus, two settings xe2x80x98measurement period and thresholdxe2x80x99 are required to determine synchronism in the viterbi decoder. When the measurement period has been changed, the threshold must also be changed.
The threshold must be changed when the coding rate has a variable length even if the measurement period is the same. The threshold is reset each time the coding rate changes (the change in the coding rate can be detected when synchronism has not been detected over a specific time. Alternatively, a scaled threshold is created by scaling a fixed value in accordance with the coding rate.
It is an object of the present invention to provide a viterbi decoder and a method for controlling synchronism in which the threshold can be appropriately and easily set in accordance with a predetermined measurement period.
A viterbi decoder according to one aspect of the present invention comprises a decoding unit which decodes input data; a coding unit which codes the data decoded by the decoding unit; a bit error corrections detecting unit which detects the number of bit error corrections in the output of the coding unit during a measurement period set externally; a synchronized state detecting unit which detects a synchronized state based on the number of bit error corrections detected by the bit error corrections detecting unit and a threshold; and a threshold detecting unit which detects the threshold based on the number of bit error corrections detected by the bit error corrections detecting unit during a preset threshold detection period that includes the measurement period.
A viterbi decoder according to another aspect of the present invention comprises a decoding unit which decodes input data; a coding unit which codes the data decoded by the decoding unit; a bit error corrections detecting unit which detects the number of bit error corrections in the output of the coding unit during a measurement period set externally; a synchronized state detecting unit which detects a synchronized state based on the number of bit error corrections detected by the bit error corrections detecting unit and a threshold; and a threshold detecting unit which, when the number of synchronous states of the viterbi decoder is 1 and the number of asynchronous states is L, measures the number of bit error corrections (L+1) times during the measurement period prior to the synchronizing operation of the viterbi decoder, and detects the threshold based on the measured number (L+1) of bit error corrections detected by the bit error corrections detecting unit.
A viterbi decoder according to still another aspect of the present invention comprises a phase rotating unit which rotates the phase of input data; a dummy symbol inserting unit which inserts a dummy symbol into the output of the phase rotating unit; a viterbi decoding unit which decodes the output of the dummy symbol inserting unit; a coding unit which codes the data decoded by the decoding unit; a bit error corrections detecting unit which detects the number of bit error corrections in the output of the coding unit during a measurement period set externally; a synchronized state detecting unit which detects a synchronized state based on the number of bit error corrections detected by the bit error corrections detecting unit and a threshold; a state storing unit for storing a state of the dummy symbol inserting unit, wherein it being possible to shift immediately to a synchronized state when the state storing unit transmits data to the dummy symbol inserting unit after a threshold detection period.
A viterbi decoder according to still another aspect of the present invention comprises a decoding unit which decodes input data; a coding unit which codes the data decoded by the decoding unit; a bit error corrections detecting unit which detects the number of bit error corrections in the output of the coding unit during a measurement period set externally; a synchronized state detecting unit which detects a synchronized state based on the number of bit error corrections detected by the bit error corrections detecting unit and a threshold; and a threshold calculating unit having register(s) and adder(s) for calculating the threshold based on the value of the measurement period.
A viterbi decoder according to still another aspect of the present invention comprises a decoding unit which decodes input data; a coding unit which codes the data decoded by the decoding unit; a bit error corrections detecting unit which detects the number of bit error corrections in the output of the coding unit during a measurement period set externally; a synchronized state detecting unit which detects a synchronized state based on the number of bit error corrections detected by the bit error corrections detecting unit and a threshold; and a scaling unit which determines the threshold by setting a ratio between the measurement period and the threshold.
A method for controlling synchronism in a viterbi decoder, the viterbi decoder comprising a decoding unit which decodes input data, and a coding unit which codes the data decoded by the decoding unit, according to still another aspect of the present invention comprises the steps of detecting the number of bit error corrections in the output of the coding unit during a measurement period set externally; detecting a synchronized state based on the detected number of bit error corrections a threshold; and detecting the number of bit error corrections in the output of the coding unit during a pre-set threshold detection period that includes the measurement period, and then detecting the threshold based on these detected number of bit error corrections.
A method for controlling synchronism in a viterbi decoder, the viterbi decoder comprising a decoding unit which decodes input data, and a coding unit which codes the data decoded by the decoding unit, according to still another aspect of the present invention comprises the steps of detecting the number of bit error corrections in the output of the coding unit during a measurement period set externally; detecting a synchronized state based on the detected number of bit error corrections a threshold; wherein, when the number of synchronous states of the viterbi decoder is 1 and the number of asynchronous states is L, the number of bit error corrections is measured (L+1) times during the measurement period prior to the synchronizing operation of the viterbi decoder; and detecting the threshold based on the measured number (L+1) of bit error corrections.
A method for controlling synchronism in a viterbi decoder, the viterbi decoder comprising a phase rotating unit which rotates the phase of input data, a dummy symbol inserting unit which inserts a dummy symbol into the output of the phase rotating unit, a viterbi decoding unit which decodes the output of the dummy symbol inserting unit, and a coding unit which codes the data decoded by the decoding unit, according to still another aspect of the present invention comprises the steps of detecting the number of bit error corrections in the output of the coding unit during a measurement period set externally; detecting a synchronized state based on the number of bit error corrections detected by the bit error corrections detecting unit and a threshold; storing a state of the dummy symbol inserting unit; and making it possible to shift immediately to a synchronized state by transmitting the stored data regarding the state to the dummy symbol inserting unit after a threshold detection period.
A method for controlling synchronism in a viterbi decoder, the viterbi decoder comprising a decoding unit which decodes input data, and a coding unit which codes the data decoded by the decoding unit, according to still another aspect of the present invention comprises the steps of detecting the number of bit error corrections in the output of the coding unit during a measurement period set externally; detecting a synchronized state based on the number of bit error corrections detected by the bit error corrections detecting unit and a threshold; calculating the threshold based on a value of the measurement period.
A method for controlling synchronism in a viterbi decoder, the viterbi decoder comprising a decoding unit which decodes input data, and a coding unit which codes the data decoded by the decoding unit, according to still another aspect of the present invention comprises the steps of detecting the number of bit error corrections in the output of the coding unit during a measurement period set externally; detecting a synchronized state based on the number of bit error corrections detected by the bit error corrections detecting unit and a threshold; determining the threshold by setting a ratio between the measurement period and the threshold as the scaling value.